A wide variety of memory devices can be used to maintain and store data and instructions for various computers and similar systems. In particular, flash memory is a type of electronic memory media that can be rewritten and that can retain content without consumption of power. Unlike dynamic random access memory (DRAM) devices and static random memory (SRAM) devices in which a single byte can be erased, flash memory devices are typically erased in fixed multi-bit blocks or sectors. Flash memory technology can include NOR flash memory and NAND flash memory, for example. NOR flash memory evolved from electrically erasable read only memory (EEPROM) chip technology, in which, unlike flash memory, a single byte can be erased; and NAND flash memory evolved from DRAM technology. Flash memory devices typically are less expensive and denser as compared to many other memory devices, meaning that flash memory devices can store more data per unit area.
Flash memory has become popular, at least in part, because it combines the advantages of the high density and low cost of electrically programmable ROM (EPROM) with the electrical erasability of EEPROM. Flash memory is nonvolatile; it can be rewritten and can hold its content without power. It can be used in many portable electronic products, such as cell phones, portable computers, voice recorders, thumbnail drives and the like, as well as in many larger electronic systems, such as cars, planes, industrial control systems, etc. The fact that flash memory can be rewritten, as well as its retention of data without a power source, small size, and light weight, have all combined to make flash memory devices useful and popular means for transporting and maintaining data.
Typically, a memory device can include data lines (e.g., Dq(0) through Dq(n−1) for an n-bit bus) that can be connected to a system bus associated with a host processor. Typically, when the memory device is first connected with a host processor, the host processor does not know the order of the data lines from the memory device, and thus does not know the bit order of the data signals being received from the memory device. As a result, if the host processor reads data from the memory device, the data can be presented by the memory device to the host processor in a scrambled order, as the host processor cannot determine which data signal is the least significant bit, which data is the most significant bit, etc.
Conventionally, in order to have the bit order of the data signals of a memory device known to other components (e.g., host processor), memory devices have been designed so that the routing of the data lines (e.g., bit lines) associated with and/or connected to the multi-bit bus are fixed. However, fixing the routing of the data lines in the memory device can result in certain constraints on the circuit layout of the memory device, which can impact the layout of other components and result in a less desirable memory device layout and/or result in a memory device that will have less density than it could otherwise have without the routing constraints.
Another conventional implementation relates to certain memory packages, such as certain dynamic random access memory (DRAM) packages. Certain DRAM packages have been designed so that the bit order of the memory device is unknown, but the data is written to or read from the memory in the same order so, since the data was written and stored in such memory device in an unknown order, the data can be read back from the memory in the same order it was written to such memory device, and as a result, other components (e.g., a host processor) can understand the data being read from such memory device.
However, certain types of memory devices, such as flash memory devices, cannot employ such a data constraint to facilitate communication of data between components. Typically, flash memory devices are structured such that the bit order of the data lines of the memory device is fixed. That is, for example, the data line for the least significant bit, Dq(0), is programmed to be Dq(0) and the data line for the most significant bit, Dq(n−1), is programmed to be Dq(n−1) during manufacturing. Further, when other components are connected to the memory device, the other components do not know which data line is associated with Dq(0), and which data line is associated with Dq(n−1) in the memory device, for instance.
It is desirable to descramble and determine the bit order of data signals and associated data lines of a memory device, so that accurate communication of data signals can be achieved between the host processor and memory device(s) as well as other components. It is further desirable to achieve descrambling of the signals in an efficient manner so as to have minimal impact on the component layout in the chip package.